Description
HDMI is far more than a video link. Consumer Electronics Control (CEC) lets every device in a home-theatre system be controlled from a single remote, and the Enhanced Audio Return Channel (eARC) carries high bit-rate, multi-channel audio from a TV back to a soundbar or AV receiver over the same HDMI cable.
The Bitec CEC and eARC IP Cores bring both functions to FPGA and ASIC designs. They complement the Bitec HDMI 2.1 IP Core, and they can also be used on their own. Each core is a compact, encrypted Verilog component with a simple 32-bit CPU register interface and interrupt. C driver libraries, simulation testbenches and hardware reference designs are included.
CEC 2.0 Features
- CEC 2.0 (HDMI 2.1) with CEC 1.x backward compatibility
- Up to two simultaneous logical addresses
- 32-byte receive and 32-byte transmit buffers
- Input noise filter
- Automatic retransmission, with ACK/NACK reporting
- Promiscuous (bus monitor) mode for debugging
- Built-in 1 kHz timer with programmable alarm interrupt
- Single clock domain, any clock frequency that is a multiple of 50 kHz
- Direct connection to an external CEC PHY (cec_in / cec_out)
- Low-level device driver plus a high-level C utility library for physical/logical address management, message building, polling and event handling
eARC / ARC Features
- eARC transmitter or receiver, selected by parameter
- Optional legacy ARC mode as a fall-back when eARC discovery fails
- Audio bit-rates from 4.096 to 98.304 Mbps
- IEC 60958-1 framing with biphase-mark encoding and falling-edge modulation on the differential audio channel
- Common-mode control (eARC data channel) with comma generation and detection
- Parallel audio sample interface or serial IEC 60958 (S/PDIF) interface
- Channel status (C bits) and parity managed by the core
- Exchange of the receiver’s audio capabilities data structure (up to 256 bytes, CTA-861-G)
- Audio latency request and reporting for lip-sync
- Hot Plug Detect handling with logical HPD status
- Built-in frequency meter and phase detector to support clock recovery
- Asynchronous mode using a fixed 300 MHz clock for PLLs that cannot lock to low bit-rates
- IEC frame and error counters for link monitoring
- Clock-enable output to power down the serial PLL when idle
CEC 2.0 IP Core
The Bitec CEC IP Core implements CEC 2.0 as specified in HDMI 2.1, with backward compatibility to CEC 1.x devices.
eARC / ARC IP Core
The Bitec eARC IP Core implements the HDMI 2.1 Enhanced Audio Return Channel and, optionally, legacy ARC (HDMI 1.4b). A single parameter selects the eARC transmitter (HDMI sink, e.g. TV) or the eARC receiver (HDMI source, e.g. soundbar or AV receiver). Legacy ARC operation uses the Bitec CEC IP Core.
The technology-dependent parts, a PLL and the eARC/ARC PHY, are instantiated outside the core so they can be tailored to each FPGA or ASIC technology. The C driver handles eARC discovery, link status, HPD, channel status, capabilities and latency through simple call-backs.
Technology Support
FPGA devices and ASIC. The IP is delivered as encrypted Verilog.
Evaluation Platform
Reference designs are available for the Altera Arria 10 and Cyclone 10 GX development kits, using the Bitec FMC HDMI 2.1 Daughter Card, which provides the eARC/ARC PHY and CEC buffering. The designs include Nios II demo software, and simulation testbenches are provided for both cores.
