HDMI 2.1 IP Core

Description

HDMI is the most widely used interconnect standard for high definition video and audio.

The Bitec HDMI 2.1 IP Core enables HDMI inter-connectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond, the Core is rich in parameterization to accommodate everything from the challenging timing closure requirements of FPGA to the power/size requirements of ASIC. CEC 2.0 and eARC/ARC are available as companion cores (Bitec CEC & eARC IP Core).

Both video and audio are supported with added low-level access to Auxiliary data packets. This feature allows low level development and testing of HDMI interfaces. It also allows a more flexible interface to the latest 3D and 8K video formats and control packets.

The core provides convenient interfacing to 3rd party SERDES for rapid development of image processing systems. It is also designed to operate in parallel with the Bitec DP 2.1 IP Core to achieve DP++ compatibility.

Technology Support: Altera/Intel GX FPGA devices, AMD/Xilinx FPGA, Microchip PolarFire FPGA, Efinix Titanium FPGA (HDMI 2.0 features), ASIC
The HDMI core supports both sink and source with top level ports for Video, Audio and AUX packets. Additional AUX data paths allow for optional InfoFrame generation and/or 2/8/32-channel Audio.

Rich parameterization allows for balanced resource and Fmax allowing the IP to target low-cost/low-performance FPGAs to full ASIC applications. All aspects of the data paths are scalable including the PIXELS/clock, FRL CHARS/clock and TMDS SYMBOLS/clock.

Optional HDCP support allows HDCP 1.4/2.3 to be applied on the TMDS data path while HDCP 2.3 only is applied to the FRL data path. The HDCP 2.3 core can be parameterized to perform hardware based authentication or CPU based authentication.

The FRL data paths for both source and sink can be parameterized to operate from 2- to 16-FRL CHARS /clk. They are designed for optimal resource usage while maintaining precise data-flow management.

When running in FRL mode an additional FRL clock is required. The clock is responsible for constructing the FRL packet data according to the HDMI 2.1 Data Flow Monitoring requirements. The Fmax of this clock can be reduced by parameterizing the core FRL data path. Such parameterizations allow FRL mode to work in low-cost FPGA devices while still achieving optimal size/power for ASIC technologies. Independent data path clocking provides convenient power save features via clock-gating strategies.

When used in parallel with the Bitec DP 2.1 IP core, DP++ based designs are achieved. DP++ allows a single DP interface connector to support both DP and HDMI connectivity.

Altera Arria 10 FPGA Evaluation Platform

Evaluation platforms are available based on the FMC HDMI 2.1 Daughter Card. Reference designs are available which demonstrate the loop-through of video from source to sink on Altera Arria 10 FPGA development kits. Reference designs for Cyclone 10, AMD/Xilinx KCU116 and Microchip PolarFire are also available on request. The example designs loop through source to sink up to 12Gbps with optional HDCP 1.4 and HDCP 2.3 support.

Efinix Titanium FPGA Evaluation Platform

An Efinix Titanium FPGA evaluation package is available in the Downloads TAB. The Efinix design supports HDMI 2.0 data rates only.

 

Optional DSC 1.2a

An optional DSC data path is available upon request as an external component. Adding DSC to HDMI 2.1 allows a much higher range of video formats. The DSC engine can be coupled to the Bitec DP 2.1 IP to ensure optimal designs by “sharing” the DSC core between DP and HDMI interfaces.