DSP solutions for industry & research

DisplayPort 1.4 IP Core

Direct connection to DisplayPort devices using the Bitec DisplayPort core.

  • 1,2 & 4 lanes
  • 1.62, 2.7, 5.4 and 8.1 Gbps link rate (includes eDP rates)
  • HDCP 1.3 / 2.2
  • MST support, up to 4 streams
  • 6, 8, 10, 12 & 16 bit color depths
  • Forward Error Correction (FEC)
  • Display Stream Compression (DSC)
  • ASIC Version available
  • Fully VESA Certified
  • etc…

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SKU: displayport-ip-core. Category: IP Cores
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Description

DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, DELL, Apple etc) DisplayPort is not hindered by license and royalty fees.

The Bitec DisplayPort IP core for Altera GX devices offers a cost-efficient alternative to ASICs and enables DTV manufacturers to rapidly develop and deliver displays offering a superior viewing experience within ever-shrinking product lifecycles.

The Bitec DisplayPort IP core accepts 1,2 or 4 lanes at either 1.62, 2.7, 5.4 or 8.1 Gbps link rate (includes eDP additional rates), in compliance with the DisplayPort 1.4 specification. Link training adaptation is performed by exploiting the reconfiguration features of Altera transceivers.

Receiver Features

  • DisplayPort 1.4 compatible (includes eDP 1.4)
  • eDP compatible
  • Support for 1,2 & 4-lanes
  • Support 1.62, 2.7, 5.4 and 8.1 Gbps link rate (includes eDP rates)
  • Support 8K60 YCbCr4:2:0 resolution
  • HDCP 1.3/2.2 (optional)
  • 6,8,10,12 & 16 bit color support
  • Supports RGB, YCbCr Colorimetric Formats
  • MCU (NiosII) managed or autonomous AUX channel
  • AUX debug channel
  • User selectable AUX register SoPC Interface
  • SoPC Integration
  • Clock Recovery support
  • DP 1.4 Multi-Stream support
  • FreeSync support
  • Global Time Code (GTC)
  • 8-Channel Audio Support
  • Forward Error Correction (FEC)
  • Display Stream Compression 1.2a (DSC) (optional)
  • Test Automation for Compliance Testing
  • ASIC Version available
  • Fully VESA Certified

Transmitter Features

  • DisplayPort 1.4 compatible (includes eDP 1.4)
  • Support for 1,2 & 4-lanes
  • Support 1.62, 2.7, 5.4 and 8.1 Gbps link rate (includes eDP rates)
  • Support 8K60 YCbCr4:2:0 resolution
  • HDCP 1.3/2.2 (optional)
  • 6,8,10,12 & 16 bit color support
  • Supports RGB, YCbCr Colorimetric Formats
  • MCU managed AUX channel
  • AUX debug channel
  • User selectable AUX register SoPC Interface
  • SoPC Integration
  • DP++ (DVI/HDMI) compatible
  • DP 1.4 Multi-Stream support
  • FreeSync support
  • Global Time Code (GTC)
  • 8-Channel Audio Support
  • Forward Error Correction (FEC)
  • Display Stream Compression 1.2a (DSC) (optional)
  • Test Automation for Compliance Testing
  • ASIC Version available
  • Fully VESA Certified
  dp_core_tx_blockdiag Video data is input to the core Transmitter as parallel data with H-sync, V-sync and Data Enable signals. Audio and secondary data streams are also supported and available for transport.

dp_core_rx_blockdiag

The core Receiver can output received video data as an Avalon-ST stream for easy integration with the Altera Image Processing Suit. Audio and all Secondary Data are available in parallel format on their respective outputs. Both Receiver and Transmitter can use optional AUX debug ports for run-time AUX message log and monitoring.

Multi-Stream (MST) applications

The Bitec DisplayPort IP Core Receiver supports Multi-Stream, a powerful DisplayPort v.1.4 feature allowing to transfer video and audio content for more than one display using only a single cable. For instance, four Full-HD streams (1920 x 1080p @ 60 Hz) can be delivered to the Receiver using Multi-Stream or a single 4K@60 stream (3840 x 2160 @ 60 Hz) using either Multi- or Single-Stream mode.

dp_core_mst_tx_blockdiag dp_core_mst_rx_blockdiag

Clock Recovery support

A Clock Recovery block is available for the Bitec DisplayPort IP Core Receiver when the application requires DisplayPort received video data to be output together with the synthesized original pixel clock. This feature is useful, for instance, for outputting HDMI and analog video without using a frame buffer. The clock recovery feature is licensed separately.

dp_core_clkrec_blockdiag

Arria 10 GX DisplayPort Evaluation kit

An evaluation kit is available to allow application development using the Bitec DisplayPort IP Core. The kit includes an Arria 10 GX development kit (Stratix V available on request), a Bitec DisplayPort FMC daughtercard and a DisplayPort cable. An Opencore evaluation Bitec DisplayPort IP Core is requried. The Opencore evaluation gives full functionality of the core under the standard Opencore terms. The Bitec DisplayPort Daughter Card allows easy interfacing to standard source and sink devices . Bitec also offer a tailoring service for bespoke designs. Contact Bitec for more details.


Various reference designs are available which demonstrate

  • Full DP 1.4 functionality
  • Link rates to 81.Gbps
  • Multistream Video Receiver and Transmitter
  • 4K@60 loopthrough
  • Pixel Clock recovery
  • DP++ using the Bitec HDMI IP Core
  • Display Stream Compression (Upon request)

 

Product Brief
IP Core and Examples (VERSION 6.3.3099)

Notes:

  • OpenCore Plus license available upon request
  • Web example designs do not support HDCP